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Microcomputer Components
8-bit CMOS Microcontroller
C505L
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Data Sheet 06.99
C505L Data Sheet Revision History: Previous Releases:
Original Version: 06.99
Page (new Page (prev. Subjects (changes since last revision) version) version) -
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For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Siemens.
Edition 06.99 Published by Infineon Technologies AG i. Gr., St.-Martin-Strasse 53 D-81541 Munchen
(c) Infineon Technologies AG 1999
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologiesis an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
8-Bit CMOS Microcontroller
C505L
Advance Information Features
* * * * * * *
Fully compatible with the standard 8051 microcontroller Superset of the 8051 architecture with 8 datapointers Up to 20 MHz operating frequency - 375 ns instruction cycle time @ 16 MHz - 300 ns instruction cycle time @ 20 MHz (50% duty cycle) Program Memory - 32K bytes of on-chip OTP memory - Externally expandable up to 64 Kbytes 256-byte on-chip RAM 256-byte on-chip XRAM Five 8-bit and one 6-bit digital I/O ports (Port 5 with 6 bits only) - Port 1 with mixed analog/digital I/O capability - Port 3 with 2 LCD output lines as secondary functions - Port 4 and 5 with 8 and 6 LCD output lines respectively as secondary functions (more features are on next page)
On-Chip Emulation Support Module
Oscillator Watchdog 10-Bit ADC Timer 2 4-Channel PWM Watchdog Timer Real-Time Clock
XRAM 256 x 8 T0 T1 CPU
RAM 256 x 8
Port 0 Port 1
8 Digit. I / O 8 Analog Inputs / 8 Digit. I / O 8 Digit. I / O 2 LCD Outputs / 8 Digit. I / O 8 LCD Outputs / 8 Digit. I / O 6 LCD Outputs / 6 Digit. I / O
MCB03832
8-Bit 8 Datapointers USART OTP 32k x 8 OTP 32k x 8 (C505L-4E only)
Port 2 Port 3 Port 4 Port 5
128-Segment LCD Control
20 LCD Outputs
Figure 1 C505L Functional Units
Data Sheet
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C505L
Features (cont'd):
* *
*
* * * * * * * *
* *
Three 16-bit timers/counters - Timer 0 / 1 (C501 compatible) - Timer 2 with 4 channels for 16-bit capture/compare operation 128-segment LCD Controller - 1/4 duty cycle drive - 4 row and 32 column outputs - On-chip programmable reference voltage generation - 20 dedicated LCD output lines (4 rows + 16 columns) Real-Time Clock - 47-bit digital clock counter - Input frequency of 32.768 KHz required - Operates in a special power down mode Full duplex serial interface with programmable baudrate generator (USART) 10-bit A/D Converter with 8 multiplexed inputs Twelve interrupt sources with four priority levels On-chip emulation support logic (Enhanced HooksTM 1)) Programmable 15-bit Watchdog Timer Oscillator Watchdog Fast power-on reset Power-saving modes - Slow-down mode - Idle mode (can be combined with slow-down mode) - 3 special power down modes - Software power-down mode with wake up capability through INT0 pin or Real-Time Clock P-MQFP-80 package Temperature ranges: SAB-C505L TA = 0 to 70 C SAF-C505L TA = - 40 to 85 C SAK-C505L TA = - 40 to 125 C (max. operating frequency: 12 MHz)
Ordering Information The ordering code for Infineon Technologies' microcontrollers provides an exact reference to the required product. This ordering code identifies:
* * *
the derivative itself, i.e. its function set the specified temperature rage the package and the type of delivery
For the available ordering codes for the C505L please refer to the "Product Information Microcontrollers", which summarizes all available microcontroller variants.
1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Infineon Technologies.
Data Sheet
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C505L
V DD
V SS
V AREF V AGND
XTAL1 XTAL2 RESET EA ALE PSEN XTAL3 XTAL4 R0 R3 C0 C31 Port 4 8-Bit Digital I / O Port 5 6-Bit Digital I / O
MCL03833
Port 0 8-Bit Digital I / O Port 1 8-Bit Digital I / O / 8-Bit Analog Inputs C505L Port 2 8-Bit Digital I / O Port 3 8-Bit Digital I / O
Figure 2 Logic Symbol
Data Sheet
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C505L
P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V DD V SS P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2 V AREF V AGND
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 39 62 38 63 37 64 36 65 35 66 34 67 33 68 32 69 31 70 C505L 30 71 29 72 28 73 27 74 26 75 25 76 24 77 23 78 22 79 80 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P2.0 / AD8 P2.1 / AD9 P2.2 / AD10 P2.3 / AD11 P2.4 / AD12 P2.5 / AD13 P2.6 / AD14 P2.7 / AD15 XTAL3 XTAL4 V DD V SS XTAL1 XTAL2 EA ALE PSEN RESET P3.0 / RxD P3.1 / TxD
P3.2 / INT0 P3.3 / INT1 P3.4 / T0 / C31 P3.5 / T1 / C30 P3.6 / WR P3.7 / RD P5.5 / C29 P5.4 / C28 P5.3 / C27 P5.2 / C26 P5.1 / C25 P5.0 / C24 P4.7 / C23 P4.6 / C22 P4.5 / C21 P4.4 / C20 P4.3 / C19 P4.2 / C18 P4.1 / C17 P4.0 / C16
R0 R1 R2 R3 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
MCP03834
Figure 3 Pin Configuration P-MQFP-80 Package (top view)
Data Sheet
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C505L
Table 1 Pin Definitions and Functions Symbol R0-R3 Pin Number 1-4 I/O*) O Function LCD Row Outputs Output of LCD controller row lines. These pins are driven by the LCD controller and drive the row input lines of the external LCD display. Enabling the LCD Controller makes these pins available for LCD output levels. R0 LCD row output 0 R1 LCD row output 1 R2 LCD row output 2 R3 LCD row output 3 These pins should not be used for input. LCD Column Outputs Output of LCD controller column lines 0 to 15. These pins are driven by the LCD controller and drive the column input lines of the external LCD display. Enabling the LCD controller makes these pins available for LCD output levels. C0 LCD column output 0 C1 LCD column output 1 C2 LCD column output 2 C3 VCCLCD column output 3 C4 LCD column output 4 C5 LCD column output 5 C6 LCD column output 6 C7 LCD column output 7 C8 LCD column output 8 C9 LCD column output 9 C10 LCD column output 10 C11 LCD column output 11 C12 LCD column output 12 C13 LCD column output 13 C14 LCD column output 14 C15 LCD column output 15 These pins should not be used for input.
1 2 3 4 C0-C15 5-20 O
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 *) I = Input O = Output
Data Sheet
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C505L
Table 1 Pin Definitions and Functions (cont'd) Symbol P4.0-P4.7 Pin Number 21-28 I/O*) I/O Function Port 4 is a 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have a 1 written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. Port 4 pins can also be configured as LCD column outputs. The secondary functions are assigned to the pins of port 4 as follows: P4.0 / C16 LCD column output 16 P4.1 / C17 LCD column output 17 P4.2 / C18 LCD column output 18 P4.3 / C19 LCD column output 19 P4.4 / C20 LCD column output 20 P4.5 / C21 LCD column output 21 P4.6 / C22 LCD column output 22 P4.7 / C23 LCD column output 23 These pins should not be used for input when configured as LCD output pins. Port 5 is a 6-bit quasi-bidirectional port with internal pull-up arrangement. Port 5 pins that have a 1 written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup transistors. Port 5 pins can also be configured as LCD column outputs. The secondary functions are assigned to the pins of port 5 as follows: P5.0 / C24 LCD column output 24 P5.1 / C25 LCD column output 25 P5.2 / C26 LCD column output 26 P5.3 / C27 LCD column output 27 P5.4 / C28 LCD column output 28 P5.5 / C29 LCD column output 29 These pins should not be used for input when configured as LCD output pins.
21 22 23 24 25 26 27 28
P5.0-P5.5
29-34
I/O
29 30 31 32 33 34
*) I = Input O = Output
Data Sheet
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C505L
Table 1 Pin Definitions and Functions (cont'd) Symbol P3.7-P3.0 Pin Number 35-42 I/O*) I/O Function Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have a 1 written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR). P3.4 and P3.5 can also be configured as LCD column outputs C31 and C30 respectively. These pins should not be used for input when configured as LCD output pins. The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 / C31 Timer 0 counter input / LCD column 31 output P3.5 / T1 / C30 Timer 1 counter input / LCD column 30 output P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory
42 41 40 39 38 37
36 35 *) I = Input O = Output
Data Sheet
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C505L
Table 1 Pin Definitions and Functions (cont'd) Symbol RESET Pin Number 43 I/O*) I Function RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal program memory (EA = 1), the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. External Access Enable This pin must be held at high level. Instructions are fetched from the internal OTP memory when the PC is less than 8000H. Instructions are fetched from external program memory, when the PC is greater than 7FFFH. This pin must not be held at low level.
PSEN
44
O
ALE
45
O
EA
46
I
*) I = Input O = Output
Data Sheet
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C505L
Table 1 Pin Definitions and Functions (cont'd) Symbol XTAL2 XTAL1 Pin Number 47 48 I/O*) O I Function XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics (refer to data Sheet) must be observed. XTAL4 Output of the inverting real-time clock oscillator amplifier. XTAL3 Input to the inverting real-time clock oscillator amplifier. To drive the real-time clock from an external clock source, XTAL3 should be driven, while XTAL4 is left unconnected. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics (refer to Data sheet) must be observed.
XTAL4 XTAL3
51 52
O I
*) I = Input O = Output
Data Sheet
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C505L
Table 1 Pin Definitions and Functions (cont'd) Symbol P2.7-P2.0 Pin Number 53-60 I/O*) I/O Function Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have a 1 written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have a 1 written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1s.
P0.7-P0.0
61-68
I/O
*) I = Input O = Output
Data Sheet
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C505L
Table 1 Pin Definitions and Functions (cont'd) Symbol P1.0-P1.7 Pin Number 71-78 I/O*) I/O Function Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs to the A/D converter. Port 1 pins that have a 1 written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being pulled low externally will source current (IIL, in the DC characteristics) because of the internal pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / INT3 / CC0 Analog input channel 0 interrupt 3 input / capture/compare channel 0 I/O P1.1 / AN1 / INT4 / CC1 Analog input channel 1/ interrupt 4 input / capture/compare channel 1 I/O P1.2 / AN2 / INT5 / CC2 Analog input channel 2 / interrupt 5 input / capture/compare channel 2 I/O P1.3 / AN3 / INT6 / CC3 Analog input channel 3 interrupt 6 input / capture/compare channel 3 I/O P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / timer 2 external reload / trigger input P1.6 / AN6 / CLKOUT Analog input channel 6 / system clock output P1.7 / AN7 / T2 Analog input channel 7 / timer/counter 2 input
71
72
73
74
75 76 77 78 *) I = Input O = Output
Data Sheet
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C505L
Table 1 Pin Definitions and Functions (cont'd) Symbol Pin Number 79 80 49, 70 50, 69 I/O*) - - - - Function Reference voltage for the A/D converter. Reference ground for the A/D converter. Ground (0 V) Power Supply (+ 5 V)
VAREF VAGND VSS VDD
*) I = Input O = Output
Data Sheet
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C505L
V DD V SS
C505L Oscillator Watchdog XRAM 256 x 8 RAM 256 x 8 OTP 32k x 8
XTAL1 OSC & Timing XTAL2 CPU 8 Datapointers Port 0 8-Bit Digit. I / O Port 1 8-Bit Digit. I / O / 8-Bit Analog In Port 2 8-Bit Digit. I / O Port 3 8-Bit Digit. I / O / 2 LCD Outputs Port 4 8-Bit Digit. I / O / 8 LCD Outputs Port 5 6-Bit Digit. I / O / 6 LCD Outputs
RESET ALE PSEN EA
Port 0
Programmable Watchdog Timer Timer 0 Timer 1 Timer 2
Port 1
Port 2
Port 3
Port 4 USART Baudrate Generator Port 5
XTAL3 XTAL4
Real-Time Clock
128-Segment LCD Controller
20 LCD Outputs
Interrupt Unit
V AREF V AGND
A / D Converter 10-Bit Emulation Support Logic
MCB03835
S&H
MUX
Figure 4 Block Diagram of the C505L Data Sheet 13 06.99
C505L
CPU The C505L is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% threebyte instructions. With a 16-MHz external clock, 58% of the instructions execute in 375 ns (20 MHz: 300 ns). Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value: 00H LSB D0H P PSW
Bit CY AC F0 RS1 RS0
Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
OV F1 P
Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
Data Sheet
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C505L
Memory Organization The C505L CPU manipulates operands in the following five address spaces: - - - - - - - up to 64 Kbytes of program memory (32K on-chip OTP memory) up to 64 Kbytes of external data memory 256 bytes of internal data memory 256 bytes of internal XRAM data memory 20 bytes of LCD Controller registers 16 bytes of Real-Time Clock (RTC) registers A 128-byte Special Function Register (SFR) area
Figure 5 illustrates the memory address spaces of the C505L.
Alternatively FFFF H Internal XRAM (256 Byte) Not used Internal LCD & RTC (36 Byte) F3DB H 8000 H 7FFF H External Data Memory Indirect Address FF H Internal RAM 80 H 7F H Internal RAM 0000 H "Code Space" "Data Space" 0000 H 00 H "Internal Data Space"
MCD03996
FFFF H
External Data Memory External
FF00 H F3FF H
F3DC H
Direct Address FF H Special Function Register 80 H
Internal (EA = 1)
Figure 5 C505L Memory Map
Data Sheet
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C505L
Reset and System Clock The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pull-down resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VDD via a capacitor. Figure 6 shows the possible reset circuitries.
VDD
+
a) C505L RESET &
b) C505L RESET
VDD
c) C505L RESET +
MCS03840
Figure 6 Reset Circuitries
Data Sheet
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C505L
Figure 7 and Figure 8 show the recommended oscillator circiutries for crystal and external clock operations, respectively, for the system or main clock.
To internal timing circuitry
XTAL2 *)
XTAL1
C505L C505
C1
C2
*) Crystal or ceramic resonator
MCS03293
Figure 7 Recommended Oscillator Circuitries (for XTAL1-XTAL2)
C505L
N.C.
XTAL2
VDD
External Clock Signal
XTAL1
MCS04037
Figure 8 Recommended Oscillator Circuitries for Real-Time Clock (XTAL3-XTAL4)
Data Sheet
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C505L
Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C505L contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function register DPSEL. Figure 9 illustrates the datapointer addressing mechanism.
----DPSEL(92 H) DPSEL .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1
.2 .1 .0 DPTR7 Selected Datapointer DPTR 0 DPTR 1 DPTR 2 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 External Data Memory
MCD00779
DPTR0 DPH(83 H ) DPL(82 H)
Figure 9 External Data Memory Addressing using Multiple Datapointers
Data Sheet
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C505L
Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip memory based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
ICE-System Interface to Emulation Hardware
SYSCON PCON TCON
RESET EA ALE PSEN
RSYSCON RPCON RTCON
EH-IC
C500 MCU
Optional I/O Ports
Port 0 Port 2
Enhanced Hooks Interface Circuit
Port 3
Port 1
RPort 2 RPort 0
TEA TALE TPSEN
Target System Interface
MCS02647
Figure 10 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Infineon Technologies.
Data Sheet
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C505L
Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area which consists of two portions: the standard special function register area and the mapped special function register area. Some of the C505L's SFRs (PCON1, VR0, VR1 and VR2) are located in the mapped SFR area. For accessing the mapped SFR area, bit RMAP in SFR SYSCON must be set. All other SFRs are located in the standard SFR area which is accessed when RMAP is cleared ("0"). The registers and data locations of the LCD Controller (LCD-SFRs) and the RTC (RTC-SFRs) are located in the external data memory area at addresses F3DDH to F3EFH and F3F0H to F3FFH respectively. Special Function Register SYSCON (Address B1H) Bit No. B1H MSB 7 _ Reset Value: XX100X01B LSB 0
6 _
5 EALE
4 RMAP
3 _
2 _
1
XMAP1 XMAP0 SYSCON
The shaded bits are not described in this section.
Bit RMAP
Function SFR map bit RMAP = 0: Access to the non-mapped (standard) SFR area is enabled. RMAP = 1: Access to the mapped SFR area is enabled. Reserved bits for future use. Read by CPU returns undefined values.
-
As long as bit RMAP is set, mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bit-addressable. The 51 SFRs in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505L are listed in Table 2 and Table 3. In Table 2 they are organized in groups which refer to the functional blocks of the C505L. The LCD and RTC-SFRs are also included in Table 2. Table 3 illustrates the contents of the SFRs in numeric order of their addresses. Table 4 lists the LCD and the RTC-SFRs in numeric order of their addresses.
Data Sheet
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C505L
Table 2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL DPSEL PSW SP SYSCON2) VR04) VR14) VR24) ADCON02) ADCON1 ADDATH ADDATL P1ANA2) IEN02) IEN12) IP02) IP1 TCON2) T2CON2) SCON2) IRCON XPAGE SYSCON2) Ports P0 P1 P1ANA2) P2 P3 P4 P5 Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte Port 1 Analog Input Selection Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register Address Contents after Reset E0H1) F0H1) 83H 82H 92H D0H1) 81H B1H FCH FDH FEH D8H1) DCH D9H DAH 90H4) A8H1) B8H1) A9H B9H 88H1) C8H1) 98H1) C0H1) 00H 00H 00H 00H XXXXX000B3) 00H 07H XX10XX01B3) C5H 85H
5)
A/DConverter
00X00000B3) 01XXX000B3) 00H 00XXXXXXB3) FFH 00H 00H 00H XX000000B3) 00H 00X00000B 00H 00H 00H XX10XX01B3) FFH FFH FFH FFH FFH 00B XX111111B
Interrupt System
XRAM
Page Address Register for Extended on-chip 91H XRAM, LCD Controller and RTC System Control Register B1H Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 4 Port 5 80H1) 90H1) 90H1) 4) A0H1) B0H1) E8H1) F8H1)
1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The content of this SFR varies with the actual step of the C505L (e.g. 01H for the first step)
Data Sheet
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C505L
Table 2 Special Function Registers - Functional Blocks (cont'd) Block Serial Channel Symbol ADCON0 2) PCON 2) SBUF SCON SRELL SRELH TCON TH0 TH1 TL0 TL1 TMOD CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON IEN02) IEN12) Name A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Power Control Register Power Control Register 1 Address Contents after Reset D8H1) 87H 99H 98H1) AAH BAH 88H1) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H1) A8H1) B8H 1) 86H A8H1) B8H1) A9H 87H 88H1) 00X00000B3) 00H XXH3) 00H D9H XXXXXX11B3) 00H 00H 00H 00H 00H 00H 00H3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B3) 00H 00H 00H 00H 00H 00H 00H 0XX0XXXXB3)
Timer 0/ Timer 1
Compare/ Capture Unit / Timer 2
Watchdog WDTREL IEN02) IEN12) IP0 2) Power Save Modes PCON 2) PCON14)
1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
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Table 2 Special Function Registers - Functional Blocks (cont'd) Block LCD Controller Symbol DAC0 LCON LCRL LCRH DIGn5) Name D/A Conversion Register LCD Control Register LCD Timer Reload Low Register LCD Timer Reload High Register LCD Digit Register `n'5) Real-Time Clock Control Register Real-Time Clock Initialization Register 0 Real-Time Clock Initialization Register 1 Real-Time Clock Initialization Register 2 Real-Time Clock Initialization Register 3 Real-Time Clock Initialization Register 4 Clock Count Register 0 Clock Count Register 1 Clock Count Register 2 Clock Count Register 3 Clock Count Register 4 Real-Time Clock Interrupt Register 0 Real-Time Clock Interrupt Register 1 Real-Time Clock Interrupt Register 2 Real-Time Clock Interrupt Register 3 Real-Time Clock Interrupt Register 4 Address Contents after Reset F3DCH F3DDH F3DEH F3DFH F3EnH F3F0H F3F1H F3F2H F3F3H F3F4H F3F5H F3F6H F3F7H F3F8H F3F9H F3FAH F3FBH F3FCH F3FDH F3FEH F3FFH 00H6) 00H6) 00H6) 00H6) 00H 5) 6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6) 00H6)
Real-Time RTCON Clock RTCR0 RTCR1 RTCR2 RTCR3 RTCR4 CLREG0 CLREG1 CLREG2 CLREG3 CLREG4 RTINT0 RTINT1 RTINT2 RTINT3 RTINT4
1) Bit-addressable SFRs 2) This SFR is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved. 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The notation "n" (n = 0 to F) in the LCD Digit Register address definition defines the number of the related LCD digit. 6) This register is located in the on-chip external data memory area.
Data Sheet
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Table 3 Contents of the SFRs, SFRs in Numeric Order of Their Addresses Addr Register Content Bit 7 after Reset1) P0 SP DPL DPH FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL TF1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
80H 2) 81H 82H 83H 86H 87H 88H2) 88H3) 89H 8AH 8BH 8CH 8DH 90H2) 90H3) 91H 92H 98H2) 99H A0H2) A8H2) A9H AAH
.6 .6 .6 .6 .6
.5 .5 .5 .5 .5 IDLS TF0 - M1 .5 .5 .5 .5 T2EX EAN5 .5 - SM2 .5 .5 ET2 .5
.4 .4 .4 .4 .4 SD TR0 WS M0 .4 .4 .4 .4 .4 EAN4 .4 - REN .4 .4 ES .4 .4
.3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 INT6 EAN3 .3 - TB8 .3 .3 ET1 .3 .3
.2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 INT5 EAN2 .2 .2 RB8 .2 .2 EX1 .2 .2
.1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 INT4 EAN1 .1 .1 TI .1 .1 ET0 .1 .1
.0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 INT3 EAN0 .0 .0 RI .0 .0 EX0 .0 .0
WDTREL 00H PCON TCON PCON1 TMOD TL0 TL1 TH0 TH1 P1 P1ANA XPAGE DPSEL SCON SBUF P2 IEN0 IP0 SRELL 00H 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH FFH 00H XXXXX000B 00H XXH FFH 00H 00H D9H
SMOD PDS TR1 EWPD - GATE .7 .7 .7 .7 T2 EAN7 .7 - SM0 .7 .7 EA .7 C/T .6 .6 .6 .6 CLKOUT EAN6 .6 - SM1 .6 .6 WDT .6
OWDS WDTS .5
1) X means that the value is undefined and the location is reserved 2) Bit-addressable SFRs 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Data Sheet
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C505L
Table 3 Contents of the SFRs, SFRs in Numeric Order of Their Addresses (cont'd) Addr Register Content Bit 7 after Reset1) P3 FFH RD - SYSCON XX10XX01B IEN1 IP1 SRELH IRCON CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON CRCL CRCH TL2 TH2 PSW 00H XX000000B XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 00H 00H 00H 00H 00H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
B0H2) B1H B8H2) B9H BAH C0H2) C1H C2H C3H C4H C5H C6H C7H C8H2) CAH CBH CCH CDH D0H2) D8H2) D9H DAH
WR -
T1 EALE
T0
INT1
INT0 - EX3 .2 - IEX3
TxD
RxD
RMAP - EX5 .4 - IEX5 EX4 .3 - IEX4
XMAP1 XMAP0 ESWI .1 .1 SWI EADC .0 .0 IADC
EXEN2 SWDT EX6 - - EXF2 - - TF2 .5 - IEX6
COCA COCAL COCA COCAL COCA COCAL COCA COCAL H3 3 H2 2 H1 1 H0 0 .7 .7 .7 .7 .7 .7 T2PS .7 .7 .7 .7 CY BD .9 .1 .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 AC CLK .8 .0 .5 .5 .5 .5 .5 .5 - .5 .5 .5 .5 F0 - .7 - .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 RS1 BSY .6 - .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 RS0 ADM .5 - .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2 OV MX2 .4 - .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 F1 MX1 .3 - .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0 P MX0 .2 -
ADCON0 00X00000B ADDATH 00H ADDATL 00XXXXXXB
1) X means that the value is undefined and the location is reserved 2) Bit-addressable SFRs
Data Sheet
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Table 3 Contents of the SFRs, SFRs in Numeric Order of Their Addresses (cont'd) Addr Register Content Bit 7 after Reset1) ADCON1 01XXX000B ACC P4 B P5 00H 00H 00H XX000000H C5H 85H
5)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DCH E0H2) E8H2) F0H2) F8H2)
ADCL1 ADCL0 - .7 .7 .7 - 1 0 .7 .6 .6 .6 - 1 0 .6 .5 .5 .5 .5 0 0 .5
- .4 .4 .4 .4 0 0 .4
- .3 .3 .3 .3 0 0 .3
MX2 .2 .2 .2 .2 1 1 .2
MX1 .1 .1 .1 .1 0 0 .1
MX0 .0 .0 .0 .0 1 1 .0
FCH3)4) VR0 FDH3)4) VR1 FEH
3)4)
VR2
1) X means that the value is undefined and the location is reserved. 2) Bit-addressable SFRs. 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual of the step C505L (e.g. 01H for the first step).
Data Sheet
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Table 4 Contents of the LCD and the RTC Registers in Numeric Order of Their Addresses Addr. Register Content Bit 7 after Reset DAC0 LCON LCRL LCRH DIGn 1) RTCON RTCR0 RTCR1 RTCR2 RTCR3 RTCR4 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H S7 DSB1 .7 SLT SEGF 0 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
F3DCH F3DDH F3DEH F3DFH F3EnH F3F0H F3F1H F3F2H F3F3H F3F4H F3F5H F3F6H F3F7H F3F8H F3F9H F3FAH F3FBH F3FCH F3FDH F3FEH F3FFH
S6 DSB0 .6 .14 0 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6 .6
S5 0 .5 .13 0 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5 .5
S4 0 .4 .12 0 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4 .4
S3 0 .3 .11 RTPD .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3 .3
S2 0 .2 .10 IRTC .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2 .2
S1 CSEL .1 .9 ERTC .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1 .1
S0 LCEN .0 .8 RTCS .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0 .0
SEGA SEGG SEGB SEGE SEGC SEGH SEGD
CLREG0 00H CLREG1 00H CLREG2 00H CLREG3 00H CLREG4 00H RTINT0 RTINT1 RTINT2 RTINT3 RTINT4 00H 00H 00H 00H 00H
1) The notation "n" (n = 0 to F) in the LCD Digit Register address definition defines the number of the related LCD digit.
Data Sheet
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C505L
Digital I/O Ports The C505L has five 8-bit and one 6-bit (port 5) digital I/O ports. Port 0 is an open-drain bidirectional I/O port, while ports 1 through 5 are quasi-bidirectional I/O ports with internal pull-up resistors. When configured as inputs, ports 1-5 will be pulled high, and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 Special Function register (SFR) contents. In this function, port 0 is not an open-drain port, but uses a strong internal pull-up. Therefore, the parallel I/O ports of the C505L can be grouped into six different types which are listed in Table 5. Table 5 C505L Port Structure Types Type A B C D E F Description Standard digital I/O ports which can also be used for external address/data bus. Standard multifunctional digital I/O port lines Mixed digital/analog I/O port lines with programmable analog input function LCD Output Lines Standard digital I/O or LCD output lines Standard multifunctional digital I/O or LCD output lines
Type A and B port pins are standard C501-compatible I/O port lines, which can be used for digital I/O. The type A ports (port 0 and port 2) are also designed for accessing external data or program memory. Type B port lines are located at port 3 (except P3.4 and P3.5), and are used for digital I/ O or for other alternate functions as described in the pin description. Type D port lines provide the LCD controller outputs R0-R3 and C0-C15 as primary functions. Type E port lines are located at port 4 and port 5 and provide the LCD controller output lines as alternate functions. Type F port lines are at P3.4/T0 and P3.5/T1 and have a digital alternate input each, apart from LCD output functions. The C505L provides eight analog input lines that are implemented as mixed digital/analog inputs (type C). The 8 analog inputs, AN0-AN7, are located at the port 1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. The analog function of the specific port 1 pins are enabled by bits in the SFRs P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog input.
Note: P1ANA is a mapped SFR and can only be accessed if bit RMAP in SFR SYSCON is set.
lf a digital value is to be read by port 1, the voltage levels are to be held within the input voltage specifications (VIL/VIH).
Data Sheet
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 6: Table 6 Timer/Counter 0 and 1 Operating Modes Mode 0 1 2 3 Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops 0 0 1 1 TMOD M1 M0 0 1 0 1 internal Input Clock external (max)
fOSC/(6 x 32)
fOSC/(12 x 32)
fOSC/6
fOSC/12
In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/6. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the input clock logic.
OSC
/6 C/T = 0
f OSC /6
Timer 0/1 Input Clock C/T = 1
P3.4/T0 P3.5/T1 TR0 TR1
_ <1
Control &
Gate (TMOD) P3.2/INT0 P3.3/INT1
=1
MCS03117
Figure 11 Timer/Counter 0 and 1 Input Clock Logic
Data Sheet
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Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C505L provides additional compare/capture/reload features, which allow the selection of the following operating modes: - Compare - Capture - Reload : up to 4 PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock) : up to 4 high speed capture inputs with 300 ns resolution : modulation of timer 2 cycle time
The block diagram in Figure 12 shows the general configuration of timer 2 with the additional compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as multifunctional port functions at port 1.
P1.5/ AN5/ T2EX P1.7/ AN7/ T2
Pin
Sync. T2I0 T2I1 EXEN2
EXF2
_ <1
Interrupt Request
Pin
Sync. & /6 Reload Reload
OSC /12 T2PS Timer 2 TL2 TH2 TF2
Compare
P1.0/ AN0/ INT3/ CC0 P1.1/ AN1/ INT4/ CC1 P1.2/ AN2/ INT5/ CC2 P1.3/ AN3/ INT6/ CC3
MCB03853
16 Bit Comparator
16 Bit Comparator
16 Bit Comparator
16 Bit Comparator
Input/ Output Control
Capture
CCL3/CCH3
CCL2/CCH2
CCL1/CCH1
CRCL/CRCH
Figure 12 Timer 2 Block Diagram Data Sheet 30 06.99
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Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation. Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The external gate signal is sampled once every machine cycle. Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. Reload of Timer 2: Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been set.
Data Sheet
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Timer 2 Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled.
Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Timer Overflow Read Pin
MCS02661
VDD
Compare Match
Internal Bus Write to Latch
S D
Q Port Latch CLK Q R
Port Pin
Figure 13 Port Latch in Compare Mode 0
Data Sheet
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Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. In compare mode 1 (see Figure 14) the port circuit consists of two separate latches. One latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs.
Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Read Pin
MCS03856
VDD
Internal Bus Compare Match Write to Latch
D Shadow Latch CLK
Q
Q Port Latch CLK Q
D
Port Pin
Figure 14 Compare Function in Compare Mode 1 Timer 2 Capture Modes Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this function. In mode 0, the external event causing a capture is: - for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1 - for the CRC register: a positive or negative transition at the corresponding pin, depending on the status of the bit I3FR in SFR T2CON. In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction. In this mode no interrupt request will be generated.
Data Sheet
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 7. Table 7 USART Operating Modes Mode 0 SCON SM0 0 SM1 0 Shift register mode, fixed baud rate Serial data enters and exits through RxD; TxD outputs the shift clock; 8-bit are transmitted/received (LSB first) 8-bit UART, variable baud rate 10 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, fixed baud rate 11 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, variable baud rate Like mode 2 Description
1 2 3
0 1 1
1 0 1
For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have to provide a "baud rate clock" (output signal in Figure 15) to the serial interface which - divided by 16 - results in the actual "baud rate". Further, the abbrevation fOSC refers to the oscillator frequency (crystal or external clock operation). The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1 or from a dedicated baud rate generator (see Figure 15).
Data Sheet
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Timer 1 Overflow Baud Rate Generator (SRELH SRELL)
ADCON0.7 (BD) 0 1 Mode 1 Mode 3
SCON.7 SCON.6 (SM0/ SM1)
/2
PCON.7 (SMOD) 0 1 Baud Rate Clock
f OSC
Mode 2 /6 Mode 0 Only one mode can be selected
MCS02733
Note: The switch configuration shows the reset state.
Figure 15 Block Diagram of Baud Rate Generation for the Serial Interface Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD. Table 8 Serial Interface - Baud Rate Dependencies Serial Interface Operating Modes Mode 0 (Shift Register) Mode 1 (8-bit UART) Mode 3 (9-bit UART) Active Control Bits Baud Rate Calculation BD - 0 1 SMOD - X X
fOSC / 6
Controlled by timer 1 overflow: (2SMOD x timer 1 overflow rate) / 32 Controlled by baud rate generator (2SMOD x fOSC) / (32 x baud rate generator overflow rate)
Mode 2 (9-bit UART)
-
0 1
fOSC / 32 fOSC / 16
Data Sheet
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LCD Controller Unit The Liquid Crystal Display (LCD) controller unit in the C505L is designed for the control of an LCD display module of 128 display segments (4 rows and 32 columns) using the 1/4 duty-cycle driving method. The C505L can be programmed to generate reference voltages for adjusting the contrast of the display. An example of a typical LCD module is shown in Figure 16. The table describes the different combinations of the row and column signals required to activate a particular segment. The signals R0-R3 and C0-C31 are the row and column signals, respectively, connected to the display module.
R3 A F R2 B
Rows
R3 R2 R1 R0 C
G
Columns C1 C0 F A G B E C D H
R1
E
D H R0 C1 C0
MCD03858
Figure 16 Organization of a Typical LCD Display Module The memory required by the LCD controller includes a control register, LCON, the D/A Converter register DAC0 and 16 individual digit registers (DIGx, x = 0 to F). These registers are implemented in the on-chip external data memory area. Accesses to these registers are similar to on-chip XRAM accesses (MOVX instructions) and therefore must be preceded by an enable operation on the onchip XRAM.
Note: The actual segment organization within the display unit could be different from the example considered here. In such cases, the segment names/positions may vary. The user should consult the manufacturer of the LCD display unit used regarding its segment organization.
The LCD outputs of the C505L must work at a frequency which is not more than 360 Hz in order to activate a display segment. To achieve this 360-Hz frequency limit, the LCD controller uses a scheme as shown in Figure 17.
Data Sheet
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C505L
.
Toggle
f RTC f OSC
1 0 CSEL
f LCDIN
15-Bit Down Counter LC14-0 SLT Underflow LC0 (Reload)
f LCD (< 360 Hz)
LC14
LCR14 LCR0 LCR14-0
f LCDIN
32.768 kHz 2 MHz 4 MHz 6 MHz 10 MHz 12 MHz 16 MHz 20 MHz
LCR (15-Bit reload)
002E H 0ADA H 15B4 H 208E H 3642 H 411C H 56D0 H 6C84 H
f LCD (in Hz)
356.17 359.97 359.97 359.97 359.97 359.97 359.97 359.97
MCD03859
Figure 17 LCD Clocking The generated LCD clock has a duty-cycle of 50%. The table in Figure 17 shows the recommended reload values at different input frequencies (fLCDIN) to generate LCD clocks of frequencies less than 360 Hz. The frequency of the LCD clock could be calculated by:
fLCD =
fLCDIN
2 x (15-bit reload value)
Hz
Data Sheet
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C505L
Display Voltage Levels The LCD controller outputs three voltage levels required for driving the LCD display module. These voltage levels are generated by a programmable 8-bit D/A converter via the register DAC0 and a resistive divider network. The D/A converter is enabled by the LCD controller enable bit LCEN (LCON.0). Any write operation to the register DAC0 with the LCD controller enabled, starts the D/A conversion and thereby the display outputs. Therefore, the C505L can be used with a wide range of LCD display modules. LCD Controller in Power Saving Mode In order to reduce power consumption, the C505L can be put into the software power down mode 2. In this mode, the LCD controller and the D/A converter do not lose their register contents and remain in operation, provided the following conditions are satisfied: - The input clock to the LCD is the 32.768 kHz real-time clock input, and - The real-time clock input at XTAL3 and XTAL4 pins is still valid.
Data Sheet
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C505L
Real-Time Clock The real-time clock unit of the C505L contains a dedicated oscillator and a 47-bit timer which is used to count time elapsed with respect to an initial time. The C505L real-time clock does not provide for any error correction. Any such corrections can be done by software only. Functionality The real-time clock can be initialized to a 40-bit initial value, which are loaded into the upper 40-bits of the timer. The lower 7 bits of the counter are never accessible by the user and merely act as prescalers that are initialized to 0000000B after a start operation on the real-time clock. One increment of the clock register is made for every cycle of the input clock (32.768 kHz). The functionality of the real-time clock is shown in Figure 18.
LSB 32.768 KHz Input
RTCR, 40-Bit Register
MSB
Control OSC. 7-Bit Timer Bit 0 Bit 6 40-Bit Comparator RTCS RTINT, 40-Bit Register IRTC Wake - up Request CLREG, 40-Bit Timer
ERTC These bits are not readable.
MCS03865
Figure 18 Real-Time Clock The register memory for the real-time clock is implemented in the on-chip external data memory area. Accesses to these registers are similar to on-chip XRAM accesses (MOVX instructions) and therefore must be preceded by an enable operation on the on-chip XRAM. These registers include the RTCON, RTCR0 to RTCR4 (RTCR), CLREG0 to CLREG4 (CLREG) and RTINT0 to RTINT4 (RTINT) registers.
Data Sheet
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C505L
Real-Time Clock in Power Saving Modes Once started in the normal mode, the oscillator as well as the whole real-time clock could remain in operation during certain power-down modes where the power supply could be reduced to a minimum of 3 V. These are the power down modes 2 and 3, where other functional units of the C505L are powered down (See "Power Saving Modes" on Page 50.). The upper 40-bit content of the real-time clock counter can be compared with the content of the programmable RTINT register in order to generate an interrupt request while the C505L is in one of software power-down modes 2 or 3, provided all of the following conditions are fulfilled: - - - - - The C505L is in one of the software power-down modes 2 or 3, Wake-up from software power-down is enabled (bit EWPD = 1 in SFR PCON1) Real-time clock wake-up source is selected (bit WS = 1 in SFR PCON1), The real-time clock interrupt is enabled (bit ERTC = 1 of RTCON), and Normally operating VDD levels are maintained
In this case, the handling is similar to the wake-up from power-down through P3.2/INT0.
Data Sheet
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C505L
10-Bit A/D Converter The C505L includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: - - - - - - - 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs 10-bit resolution Single or continuous conversion mode Internal start-of-conversion trigger capability Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built-in hidden calibration of offset and linearity errors
The 10-bit ADC uses two clock signals for operation: the conversion clock fADC (= 1/tADC) and the input clock fIN (= 1/tIN). fADC is derived from the C505L system clock fOSC which is applied at the XTAL pins. The input clock fIN is equal to fOSC The conversion fADC clock is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.
ADCL1
ADCL0
f OSC
/ 32 / 16 /8 /4 Clock Prescaler Input Clock f IN Conditions: MUX Conversion Clock f ADC A/D Converter
f ADC max = 2 MHz
f IN = f OSC =
1 CLP
MCS03867
MCU System Clock fIN Rate (fOSC) [MHz] 2 MHz 6 MHz 8 MHz 12 MHz 16 MHz 20 MHz 2 6 8 12 16 20
Prescaler Ratio /4 /4 /4 /8 /8 / 16
fADC
[MHz] 0.5 1.5 2 1.5 2 1.25
ADCL1 0 0 0 0 0 1
ADCL0 0 0 0 1 1 0
Figure 19 10-Bit A/D Converter Clock Selection Data Sheet 41 06.99
C505L
IEN1 (B8 H ) EXEN2 SWDT SWDT EX6 EX5 EX4 EX3 ESW1 EADC
Internal Bus
IRCON (C0 H ) EXF2 P1ANA (90 H ) EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC
ADCON1 (DC H ) ADCL1 ADCL2 MX2 MX1 MX0
ADCON0 (D8 H ) BD CLK BSY ADM MX2 MX1 MX0
Port 1 MUX S&H Clock Prescaler 32, 16, 8, 4
Single / Continuous Mode
ADDATH ADDATL (D9 H ) (DA H ) .2 .3 .4 .5 .6 .7 .8 MSB LSB .1
f OSC
Conversion Clock f ADC Input Clock f IN
A/D Converter
V AREF V AGND
Start of conversion
Internal Bus Write to ADDATL Shaded Bit locations are not used in ADC - functions.
MCB03866
Figure 20 Block Diagram of the 10-Bit A/D Converter Data Sheet 42 06.99
C505L
Interrupt System The C505L provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter) and six interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.0/AN0/INT3/CC0, P1.1/AN1/ INT4/CC1, P1.2/AN2/INT5/CC2, P1.3/AN3/INT6/CC3). Additionally, the P1.5/AN5/T2EX can trigger an interrupt. There is one software-generated interrupt (bit SWI in SFR IEN1) in addition to the above interrupts. The wake-up from power-down mode interrupt has a special functionality which allows an exit from the software power-down mode by a short low pulse at either pin P3.2/ INT0 or by the real-time clock interrupt. Figure 21 to Figure 23 give a general overview of the interrupt sources and illustrate the corresponding request and the control flags. Table 9 lists all interrupt sources with the corresponding request flags and interrupt vector addresses. Table 9 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload A/D Converter Software Interrupt External interrupt 3 External Interrupt 4 External Interrupt 5 External interrupt 6 Wake-up from power-down mode Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 007BH Interrupt Request Flags IE0 TF0 IE1 TF1 RI / TI TF2 / EXF2 IADC SWI IEX3 IEX4 IEX5 IEX6 IRTC (real-time clock wake-up only)
Data Sheet
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C505L
Highest Priority Level P3.2 / INT0 IT0 TCON.0 A / D Converter IADC IRCON.0 EADC IEN1.0 IE0 TCON.1 EX0 IEN0.0 0003 H Lowest Priority Level P o l l i n g S e q u e n c e
0043 H IP1.0 IP0.0
Timer 0 Overflow
TF0 TCON.5 ET0 IEN0.1 000B H
Software Interrupt
SWI IRCON.1 ESWI IEN1.1
004B H
Bit addressable Request flag is cleared by hardware
EA IEN0.7
IP1.1
IP0.1
MCB03869
Figure 21 Interrupt Structure, Overview Part 1
Data Sheet
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C505L
Highest Priority Level P3.3 / INT1 IT1 TCON.2 P1.0 / AN0 / INT3 / CC0 I3FR T2CON.6 Timer 1 Overflow TF1 TCON.7 P1.1 / AN1 / INT4 / CC1 ET1 IEN0.3 IEX4 IRCON.3 EX4 IEN1.3 EA Bit addressable Request flag is cleared by hardware IEN0.7
MCB03304
IE1 TCON.3 EX1 IEN0.2 IEX3 IRCON.2 EX3 IEN1.2
0013 H Lowest Priority Level P o l l i n g S e q u e n c e IP1.3 IP0.3
0053 H IP1.2 IP0.2
001B H
005B H
Figure 22 Interrupt Structure, Overview Part 2
Data Sheet
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C505L
RI USART SCON.0 TI P1.2 / AN2 / INT5 / CC2 SCON.1
>1 ES IEN0.4 IEX5 IRCON.4 EX5 IEN1.4 0063 H IP1.4 IP0.4 0023 H
Highest Priority Level
Lowest Priority Level P o l l i n g S e q u e n c e IP1.5 IP0.5
Timer 2 Overflow P1.5 / AN5 / T2EX P1.3 / INT6 / CC3
TF2 IRCON.6 EXF2
EXEN2
>1 ET2 IEN0.5 IEX6 002B H
IRCON.7
IEN1.7 IRCON.5 EX6 IEN1.5 EA Bit addressable Request flag is cleared by hardware IEN0.7 006B H
MCB03305
Figure 23 Interrupt Structure, Overview Part 3
Data Sheet
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C505L
Fail Save Mechanisms The C505L offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: - a programmable watchdog timer (WDT), with variable time-out period from 192 s up to approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz). - an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. The watchdog timer in the C505L is a 15-bit timer, which is incremented by a count rate of fOSC/12 up to fOSC/192. The system clock of the C505L is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.
0
7 WDTL 14 8 WDTH
f OSC / 6
2
16
WDT Reset - Request IP0 (A9 H )
OWDS WDTS
WDTPSEL
External HW Reset 76 WDTREL (86 H ) Control Logic WDT
SWDT
0
IEN0 (A8 H ) IEN1 (B8 H )
MCB03306
Figure 24 Block Diagram of the Watchdog Timer The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped during active mode of the device. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. Data Sheet 47 06.99
C505L
Oscillator Watchdog The oscillator watchdog unit serves for four functions: - Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. - Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. - Control of wake-up from software power-down mode When the software power-down mode is left by a low level at the P3.2/INT0 pin or an active Real-Time Clock Interrupt Request flag IRTC, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the onchip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. Note: The oscillator watchdog unit is always enabled.
Data Sheet
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C505L
EWPD IRTC (RTCON.2) P3.2 / INT0 Control Logic
WS
Power - Down Mode Activated
(PCON1.0) Power - Down Mode Wake - Up Interrupt Control Logic Internal Reset
Start / Stop RC Oscillator
f RC
3 MHz Start / Stop
10
f1
Frequency Comparator
f 2 Delay
>1
XTAL2 XTAL1 On-Chip Oscillator
f2
IP0 (A9 H )
OWDS
Int. Clock
MCB03870
Figure 25 Block Diagram of the Oscillator Watchdog
Data Sheet
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C505L
Power Saving Modes The C505L provides three basic power saving modes, the idle mode, the slow-down mode and the software power down mode. - Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset. - Slow down mode The controller remains fully functional, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32 of their normal operating frequency and also reduces power consumption. - Software power down modes: Software power-down mode 1, in which all the peripheral blocks and the CPU are stopped. This mode is used to save contents of internal RAM, XRAM and SFRs with a very low standby current. Software power-down mode 2, in which only the Real-time clock and LCD controller are operating. In this mode, the CPU and the rest of the peripherals are stopped. The RC oscillator and the on-chip oscillator are stopped, the real-time clock oscillator that operates with the XTAL3 and XTAL4 pins is still running and the real-time count is maintained in this mode. Software power-down mode 3, in which only the real-time clock is operating. In this mode, the clock input into the CPU, LCD controller and the rest of the peripherals are stopped. The only difference between this mode and mode 2 is that the LCD controller is also stopped in this mode. In all the software power-down modes, VDD can be reduced to minimize power consumption. In the case of the software power-down mode 3, VDD can be reduced to 3 V (lower specification limit). It must be ensured, however, that VDD is not reduced before any of the power-down modes is invoked, and that VDD is restored to its normal operating level before leaving the power-down mode. Any of these software power-down modes can be exited either by an active reset signal or by a wake-up request. Using reset to leave power-down mode puts the microcontroller with its SFRs into the reset state. Program execution then starts from the address 0000H. Using a wake-up request to exit the power-down mode starts the RC oscillator and the on-chip oscillator and maintains the state of the SFRs, which were frozen when power-down mode was entered. When the C505L is in software power-down mode 1, a wake-up operation is possible only through P3.2/INT0. There are two ways to use a wake-up request to exit power-down modes 2 and 3: - Wake-up via P3.2/INT0 pin, or - Wake-up via the real-time clock interrupt
Data Sheet
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C505L
Table 10 Power Saving Modes Overview Mode Entering Sequence Example ORL PCON, #01H ORL PCON, #20H Leaving by Remarks
Idle mode
Occurrence of an interrupt from a peripheral unit Hardware Reset
CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Internal clock rate is reduced to 1/32 of its nominal frequency CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with 1/32 of its nominal frequency Oscillator is stopped; contents of on-chip RAM, XRAM and SFR's are maintained;
Slow Down Mode
In normal mode: ORL PCON, #10H With idle mode: ORL PCON, #01H ORL PCON, #30H
ANL PCON,#0EFH Hardware Reset Occurrence of an interrupt from a peripheral unit Hardware reset
Software ... Power Down Mode1 bit LCEN (LCON register) is cleared; bit RTPD (RTCON register) is set; ORL PCON, #02H ORL PCON, #40H Software ... Power Down Mode 2 bits LCEN and CSEL (LCON register) are set, bit RTPD (RTCON register) is cleared; ... ORL PCON, #02H ORL PCON, #40H Software ... Power Down Mode 3 bit LCEN (LCON register) is cleared; bit RTPD (RTCON register) is cleared; ... ORL PCON, #02H ORL PCON, #40H
Short low pulse at pin P3.2/INT0 Hardware Reset
Short low pulse at pin P3.2/INT0 or real-time clock wake-up interrupt Hardware Reset
Oscillator is stopped; contents of on-chip RAM, XRAM and SFR's are maintained; LCD Controller and real-time clock are functioning
Short low pulse at pin P3.2/INT0 or real-time clock wake-up interrupt Hardware Reset
Oscillator is stopped; contents of on-chip RAM, XRAM and SFR's are maintained; real-time clock is functioning
Data Sheet
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C505L
OTP Memory Operation The C505L contains a 32 Kbyte one-time programmable (OTP) program memory. With the C505L fast programming cycles are achieved (1 byte in 100 s). Also several levels of OTP memory protection can be selected. For programming of the device, the C505L must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C505L operates as a slave device similar as an EPROM stand-alone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. Figure 26 shows the pins of the C505L which are required for controlling of the OTP programming mode.
VDD
VSS
P2.0-7 PALE PMSEL0 PMSEL1
Port 2
Port 0
P0.0-7 EA/VPP PROG PRD
C505L
RESET XTAL1 XTAL2 PSEN PSEL
MCL04038
Figure 26 Programming Mode Configuration
Data Sheet
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C505L
Pin Configuration in Programming Mode
A0 / A8 A1 / A9 A2 / A10 A3 / A11 A4 / A12 A5 / A13 A6 / A14 A7 N.C. N.C. V DD V SS XTAL1 XTAL2 EA / V PP PROG PSEN RESET PMSEL0 PMSEL1
D7 D6 D5 D4 D3 D2 D1 D0
60 61
55
50
45
41 40
65 35
V DD V SS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
70
C505L P - MQFP - 80 Package
30
75
25
80
1
5
10
15
21 20
PSEL PRD PALE N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
MCP03877
Figure 27 P-MQFP-80 Pin Configuration of the C505L in Programming Mode (top view)
Data Sheet
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C505L
Table 11 is a functional description of all C505L pins that are required for OTP memory programming. Table 11 Pin Definitions and Functions of the C505L in Programming Mode Symbol RESET Pin Number P-MQFP-80 43 I Reset This input must be at static "1" (active) level during the whole programming mode. Programming Mode SELection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL1 0 0 1 1 PSEL 40 I PMSEL0 0 1 0 1 Access Mode Reserved Read signature bytes Program/read lock-bits Program/read OTP memory byte I/O *) Function
PMSEL0 PMSEL1
42 41
I I
Basic Programming Mode SELect This input is used for the basic programming mode selection and must be switched according to Figure 28. Programming mode ReaD strobe This input is used for read access control for OTP memory read, version byte read, and lock-bit read operations. Programming Address Latch Enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at a low level when the logic level of PMSEL1,0 is changed. XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the oscillator amplifier.
PRD
39
I
PALE
38
I
XTAL2 XTAL1
47 48
O I
*) I = Input O = Output
Data Sheet
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C505L
Table 11 Pin Definitions and Functions of the C505L in Programming Mode (cont'd) Symbol Pin Number P-MQFP-80 49, 70 50, 69 60-53 I/O *) Function - - I Circuit ground potential Must be applied in programming mode. Power supply terminal Must be applied in programming mode. Address lines Multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. Program Store ENable This input must be at static "0" level during the whole programming mode. PROGramming mode write strobe This input is used in programming mode as a write strobe for OTP memory program, and lock-bit write operations. During basic programming mode selection a low level must be applied to PROG. Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock-bit. During an OTP memory read operation, this pin must be at VIH high level. This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA/VPP. Data lines 0-7 During programming mode, data bytes are transferred via the bidirectional D7-D0 lines that are located at port 0 pins. Not Connected These pins should not be connected in programming mode.
VSS VDD
A0-A7, A8-A14 (Port 2) PSEN
44
I
PROG
45
I
EA/VPP
46
-
D7-D0 (Port 0) N.C.
68-61
I/O
1-37, 51-52, 71-80
-
*) I = Input O = Output
Data Sheet
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C505L
Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 28.
V DD
Clock (XTAL1 / XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE "0" "0" "1" 0,1 Stable "1" "0"
5V
V PP
EA / V PP During this period signals are not actively driven 0V
V IH2
Ready for access mode selection
MCS03878
Figure 28 Basic Programming Mode Selection
Data Sheet
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C505L
Table 12 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte EA/
VPP VPP VIH VPP VIH VIH
PROG
PRD H
PMSEL 1 H H L 0 H L H
Address (Port 2) A0-7 A8-14 -
Data (Port 0) D0-7 D1,D0 see Table 13
H H H H
Byte addr. D0-7 of sign. byte
Lock Bits Programming / Read The C505L has two programmable lock-bits that, when programmed according to Table 13, provide four levels of protection for the on-chip OTP code memory. Table 13 Lock Bit Protection Types Lock Bits at D1,D0 D1 1 1 D0 1 0 Protection Protection Type Level Level 0 Level 1 The OTP lock feature is disabled. During normal operation of the C505L, the state of the EA pin is not latched on reset. During normal operation of the C505L, MOVC instructions executed from external program memory are prevented from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible in the OTP verification mode. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but OTP memory read operation using OTP verification mode is disabled. Same as level 2, but external code execution by setting EA = low during normal operation of the C505L is not possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the OTP memory boundary), is still possible.
0 0
1 0
Level 2 Level 3
Note: A "1" means that the lock-bit is not programmed. A "0" means that lock-bit is programmed.
Data Sheet
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C505L
Version Bytes The steppings of the C505L versions will contain the following version register/byte information: Stepping C505L CA-Step Version Byte 0 = VR0 Version Byte 1 = VR1 Version Byte 2 = VR2 (mapped addr. FCH) (mapped addr. FDH) (mapped addr. FEH) C5H 85H 04H
Note: Future steppings of C505L would have a different version byte 2 content.
Data Sheet
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C505L
Absolute Maximum Ratings Parameter Storage temperature Symbol min. Limit Values max. 150 6.5 C V V mA mA W - - - - - - - 40 - 0.5 - 0.5 - 10 Unit Notes
TST
Voltage on VDD pins with respect VDD to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition
VIN
VDD + 0.5
10 | 100 mA | 1
-
Absolute sum of all input currents - during overload condition Power dissipation
- -
PDISS
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
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C505L
Operating Conditions Parameter Supply Voltage (Normal mode) Supply Voltage (Software Power down mode 3 only) Ground voltage Ambient temperature SAB-C505L SAF-C505L SAK-C505L Analog reference voltage Analog ground voltage Analog input voltage CPU clock Symbol min. Limit Values max. 5.5 V V - Not during wake-up sequence. - - Unit Notes
VDD
4.25
3
VSS TA TA TA VAREF VAGND VAIN fCPU
0 - 40 - 40 4
0 70 85 125
V C
VDD + 0.1 VSS + 0.2 VAREF
20
V V V
- - -
VSS - 0.1 VAGND
2
MHz -
Data Sheet
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C505L
DC Characteristics (Operating Conditions apply) Parameter Input low voltages all except EA, RESET, XTAL3 EA pin RESET pin XTAL3 Input high voltages except XTAL1, RESET, XTAL3 and EA XTAL1 RESET, EA XTAL3 Output low voltages Ports 1, 2, 3, 4, 5 Port 0, ALE, PSEN Output high voltages Ports 1, 2, 3, 4, 5 Port 0 in external bus mode, ALE, PSEN Logic 0 input current Ports 1, 2, 3, 4, 5 Logical 0-to-1 transition current Ports 1, 2, 3, 4, 5 Input leakage current Port 0, AN0-7(Port 1), EA Pin capacitance Overload current Programming voltage Supply current at EA/VPP Notes see Page 63. Symbol min. Limit Values max. 0.2 VDD - 0.1 0.2 VDD - 0.3 0.2 VDD + 0.1 0.7 VDD V V V V V V V V V V V V V V A A - - - - - - - - Unit Test Condition
VIL VIL1 VIL2 VIL3 VIH VIH1 VIH2 VIH3 VOL VOL1 VOH VOH2
- 0.5 - 0.5 - 0.5 - 0.5 0.2 VDD + 0.9 0.7 VDD 0.6 VDD 0.9 VDD - - 2.4 0.9 VDD 2.4 0.9 VDD - 10 - 65
VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5
0.45 0.45 - - - - - 70 - 650
IOL = 1.6 mA1) IOL = 3.2 mA1) IOH = - 80 A IOH = - 10 A IOH = - 800 A2) IOH = - 80 A2) VIN = 0.45 V VIN = 2 V
IIL ITL
ILI CIO IOV VPP
-
- - - 10.9 -
1 10
A pF mA
0.45 < VIN < VDD
fc = 1 MHz, TA = 25 C
8) 9)
5
12.1 30
V mA
11.5 V 5%12)
12)
Data Sheet
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C505L
Power Supply Current (Operating Conditions apply) Parameter Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled 16 MHz 20 MHz 16 MHz 20 MHz 16 MHz 20 MHz 16 MHz 20 MHz Symbol Limit Values typ.10) max.11) 36.6 43.0 19.4 22.0 7.6 8.1 7.5 8.0 50 300 50 mA mA mA mA
4)
Unit Test Condition
IDD IDD IDD IDD IDD IDD IDD IDD IPD1 IPD2 IPD3
28.7 34.0 13.7 15.9 5.7 6.2 4.7 4.9 20 250 20
5)
6)
7)
Power down current: Software Power-down mode 1 Software Power-down mode 2 Software Power-down mode 3 Notes see next page.
A A A
VDD = 2...5.5 V3) VDD = 4.25 - 5.5 V3) VDD = 3...5.5 V3)
Data Sheet
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06.99
C505L
Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing. 3) Power-down modes: IPD1 is measured under following conditions: EA = Port 0 = V DD ; RESET = V SS .; XTAL2 = XTAL4 = N.C.; XTAL1 = XTAL3 =V SS ; V AGND = V SS ; VAREF = VDD ; all other pins are disconnected. Conditions for IPD2 and IPD3 are similar except that XTAL3 and XTAL4 have a valid input from the 32.768 KHz crystal and the power supply limits. 4) IDD (active mode) is measured with: XTAL1 driven with t R /t F = 5 ns, 50% duty cycle , V IL = V SS + 0.5 V, V IH = V DD - 0.5 V; XTAL2 = N.C.; EA = Port0 = RESET = VDD; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (approx. 1 mA) 5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR/tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VDD ; all other pins are disconnected; the microcontroller is put into idle mode by software; 6) IDD (active mode with slow-down) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR/tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; all other pins are disconnected; the microcontroller is put into slow-down mode by software; 7) IDD (idle mode with slow-down) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR/tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VDD ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software; 8) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5V or VOV < VSS - 0.5V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits. 9) Not 100% tested, guaranteed by design characterization 10) The typical IDD values are periodically measured at TA = + 25 C but not 100% tested. 11) The maximum IDD values are measured under worst case conditions (TA = 0 C or - 40 C and VDD = 5.5 V) 12) Only valid in programming mode.
Data Sheet
63
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C505L
50 mA
MCD04040
DD
40
DD max DD typ
Mod e
e
e Activ
30
e Activ
20
Mod
Idle Mode
Idle Mode
Slow Down Mode Slow Down Mode
10
0
0
4
8
12
16
MHz
20
f OSC
Figure 29 IDD Diagram Table 14 Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Symbol Formula 1.33 x fOSC + 7.33 1.61 x fOSC + 10.8 0.54 x fOSC + 5.07 0.66 x fOSC + 8.83 0.12 x fOSC + 3.87 0.12 x fOSC + 5.77 0.05 x fOSC + 3.9 0.12 x fOSC + 5.67
IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max
Note: 1. fOSC is the oscillator frequency in MHz. IDD values are given in mA. 2. IDD graph for idle mode with slow-down enabled is not shown since it is very similar to active mode with slow-down enabled.
Data Sheet
64
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C505L
LCD-Output Characteristics (Operating Conditions apply) Parameter Full range output voltage, of D/A Converter Symbol min. Limit Values typ. - max. 4.75 7% 0 Unit Test Condition V V Normal mode VDD range (operating conditions)
VO
Settling Time of D/A Converter Output DC differential non-linearity of D/A Converter DC integral non-linearity of D/A Converter DC Offset Voltage of D/A Converter LCD Voltage levels
tSET
DNL INL -
- - - - -
- - - -
350 1 6 15 -
S
VDD = 5 V
LSB - % mV V
VDD = 5 V
-
1)
VLCD1 VLCD2 VLCD3
VO
2 x VO/3 VO/3
Note: 1) Conditions as in VO apply.
Data Sheet
65
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C505L
A/D Converter Characteristics (Operating Conditions apply) Parameter Analog input voltage Sample time Symbol Limit Values min. max. V ns
1)
Unit
Test Condition
VAIN tS
VAGND VAREF
- 64 x tIN 32 x tIN 16 x tIN 8 x tIN 384 x tIN 192 x tIN 96 x tIN 48 x tIN 2 4
Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 42) Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 43)
Conversion cycle time
tADCC
-
ns
Total unadjusted error
TUE
- -
LSB LSB
VSS + 0.5 V VAIN VDD - 0.5 V4) VSS < VAIN < VDD + 0.5 V VDD - 0.5 V < VAIN < VDD4) tADC in [ns] 5) 6) tS in [ns] 2) 6)
Internal resistance of RAREF reference voltage source Internal resistance of analog source
Notes see next page.
- -
tADC / 250 k
- 0.25
RASRC
tS / 500
- 0.25
k
Clock Calculation Table: Clock Prescaler Ratio / 32 / 16 /8 /4 ADCL1, 0 1 1 0 0 1 0 1 0
tADC
32 x tIN 16 x tIN 8 x tIN 4 x tIN
tS
64 x tIN 32 x tIN 16 x tIN 8 x tIN
tADCC
384 x tIN 192 x tIN 96 x tIN 48 x tIN
Further timing conditions: tADC min = 500 ns tIN = 1 / fOSC = tCLP
Data Sheet
66
06.99
C505L
Notes: 1)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively.
2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization.
Data Sheet
67
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C505L
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 16-MHz clock Duty Cycle 0.4 to 0.6 min. ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in max. - - - 75 - - 38 - 15 - 95 - Limit Values Variable Clock 1/CLP= 2 MHz to 16 MHz min. CLP - 15 TCLHmin - 15 TCLHmin - 15 - TCLLmin - 15 CLP+ TCLHmin - 15 - 0 - TCLLmin - 5 - -5 max. - - - 2 CLP - 50 - - CLP + TCLHmin- 50 - TCLLmin - 10 - 2 CLP + TCLHmin - 55 - ns ns ns ns ns ns ns ns ns ns ns ns Unit
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV
48 10 10 - 10 73 - 0 - 20 - -5
Input instruction hold after PSEN tPXIX Input instruction float after PSEN tPXIZ*) Address valid after PSEN Address to valid instruction in Address float to PSEN
*)
tPXAV*) tAVIV tAZPL
Interfacing the C505L to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Data Sheet
68
06.99
C505L
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (cont'd) External Data Memory Characteristics Parameter Symbol 16-MHz clock Duty Cycle 0.4 to 0.6 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 100 - 51 200 200 103 - 40 - - - 0 Limit Values Variable Clock 1/CLP= 2 MHz to 16 MHz min. 3 CLP - 30 3 CLP - 30 CLP - 15 - 0 - - - CLP + TCLLmin - 15 2 CLP - 30 TCLHmin - 15 TCLLmin - 20 3 CLP + TCLLmin - 50 - max. - - - 2 CLP + TCLHmin - 50 - CLP - 12 4 CLP - 50 4 CLP + TCLHmin - 75 CLP+ TCLLmin + 15 - TCLHmin + 15 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
158 158 48 - 0 - - - 73 95 10 5 163 5 -
TCLHmin - 20 - 0
Data Sheet
69
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C505L
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (cont'd) External Clock Drive Characteristics Parameter Symbol CPU Clock = 16 MHz Duty Cycle 0.4 to 0.6 min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle CLP TCLH TCLL 62.5 25 25 - - 0.4 25 max. 62.5 - - 10 10 0.6 37.5 Variable CPU Clock 1/CLP = 2 to 16 MHz min. 62.5 25 25 - - 25 / CLP CLP x DCmin max. 500 CLP - TCLL CLP - TCLH 10 10 1 - 25 / CLP ns ns ns ns ns - Unit
tR tF
DC TCL
CLP x DCmax ns
Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6.
Data Sheet
70
06.99
C505L
AC Characteristics (20 MHz, 0.5 Duty Cycle) (Operating Conditions apply)
CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics Parameter Symbol Limit Values 20 MHz clock Variable Clock 0.5 Duty Cycle 1/CLP = 2 MHz to 20 MHz min. ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
*)
Unit
max. - - - 55 - - 25 - 20 - 65 -
min. CLP - 15 CLP/2 - 15 CLP/2 - 15 - CLP/2 - 15 3/2 CLP - 15 - 0 - CLP/2 - 5 - -5
max. - - - 2 CLP - 45 - - 3/2 CLP - 50 - CLP/2 - 5 - 5/2 CLP - 60 - ns ns ns ns ns ns ns ns ns ns ns ns
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL
35 10 10 - 10 60 - 0 - 20 - -5
Interfacing the C505L to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Data Sheet
71
06.99
C505L
AC Characteristics (20 MHz, 0.5 Duty Cycle) (cont'd)
External Data Memory Characteristics Parameter Symbol 20 MHz clock 0.5 Duty Cycle min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 75 - 38 150 150 90 - 40 - - - 0 Limit Values Variable Clock 1/CLP = 2 MHz to 20 MHz min. 3 CLP - 30 3 CLP - 30 CLP - 15 - 0 - - - 2 CLP - 30 CLP/2 - 15 CLP/2 - 20 CLP/2 - 20 - max. - - - 5/2 CLP- 50 - CLP - 12 4 CLP - 50 ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
120 120 35 - 0 - - - 60 70 10 5 125 5 -
9/2 CLP - 75 ns - CLP/2 + 15 - - 0 ns ns ns ns ns ns
3/2 CLP - 15 3/2 CLP + 15 ns
7/2 CLP - 50 -
External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 2 MHz to 20 MHz min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle CLP TCLH TCLL 50 15 15 - - 0.5 max. 500 CLP - TCLL CLP - TCLH 10 10 0.5 ns ns ns ns ns - Unit
tR tF
DC
Data Sheet
72
06.99
C505L
t LHLL
ALE
t AVLL t LLPL t LLIV t PLIV
PSEN
t PLPH
t AZPL t LLAX
t PXAV t PXIZ t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 30 Program Memory Read Cycle
Data Sheet
73
06.99
C505L
t WHLH
ALE
PSEN
t LLDV t LLWL
RD
t RLRH
t RLDV t AVLL t LLAX2 t RLAZ
Port 0 A0 - A7 from Ri or DPL Data IN
t RHDZ t RHDX
A0 - A7 from PCL Instr. IN
t AVWL t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 31 Data Memory Read Cycle
Data Sheet
74
06.99
C505L
t WHLH
ALE
PSEN
t LLWL
WR
t WLWH
t QVWX t AVLL t LLAX2
A0 - A7 from Ri or DPL
t WHQX t QVWH
Data OUT A0 - A7 from PCL Instr.IN
Port 0
t AVWL
Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH
MCT00098
Figure 32 Data Memory Write Cycle
TCL H
tR
tF
XTAL1 TCL L CLP
0.7 V DD 0.2 V DD - 0.1
MCT03310
Figure 33 External Clock Drive on XTAL1
Data Sheet
75
06.99
C505L
AC Characteristics of Programming Mode
VDD = 5 V 10 %; VPP = 11.5 V 5 %; TA = 25 C 10 C
Parameter PALE pulse width PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD falling edge Address hold after PALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width PRD pulse width Address to valid data out PRD to valid data out Data hold after PRD Data float after PRD Symbol min. Limit Values max. - - - - - - - - - - 75 20 - 20 - - 500 ns - ns ns ns ns ns ns s ns ns ns ns ns s ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 83.3 Unit
tPAW tPMS tPAS tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF
PROG high between two consecutive PROG tPWH1 low pulses PRD high between two consecutive PRD low tPWH2 pulses XTAL clock period
tCLKP
Data Sheet
76
06.99
C505L
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A14
t PAH
A0-A7
Port 0
D0-D7
PROG
t PWH t PCS t PWW t PCH
MCT03642
Notes: PRD must be high during a programming write cycle.
Figure 34 Programming Code Byte - Write Cycle Timing
Data Sheet
77
06.99
C505L
t PAW
PALE
t PMS
PMSEL1,0 H, H
t PAS
Port 2 A8-A14
t PAH
A0-A7
t PAD
Port 0 D0-D7
t PDH
t PRD
PRD
t PDF t PWH
t PCS
Notes: PROG must be high during a programming read cycle.
t PRW
t PCH
MCT03643
Figure 35 Verify Code Byte - Read Cycle Timing
Data Sheet
78
06.99
C505L
PMSEL1,0
H, L
H, L
Port 0
D0, D1
D0, D1
t PCS t PMS
PROG
t PCH t PMH t PDH t PWW t PMS t PRD t PRW t PMH t PDF
PRD Note: PALE should be low during a lock bit read / write cycle.
MCT03644
Figure 36 Lock Bit Access Timing
PMSEL1,0
L, H
Port 2
e. g. FD H
t PCH
Port 0 D0-7
t PCS t PRD t PMS
PRD
t PDH t PDF t PMH
t PRW
MCT03645
Note: PROG must be high during a programming read cycle.
Figure 37 Version Byte Read Timing
Data Sheet
79
06.99
C505L
OTP Verification Mode Characteristics
Note: ALE pin described below is the pin 45.
Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ. CLP 6 CLP - - TCLH - max. - - 2 CLP - - 6 ns ns ns ns ns MHz - - - 4 CLP - 4 Unit
tAWD tACY tDVA tDSA tAS
1/ CLP
t ACY t AWD
ALE
t DSA t DVA
Port 0 Data Valid
t AS
P3.5
MCT02613
Figure 38 OTP Verification Mode
Note: This mode cannot be entered if OTP protection levels of 1 to 3 are programmed.
Data Sheet
80
06.99
C505L
V DD -0.5 V
0.2 VDD +0.9 Test Points 0.2 VDD -0.1
MCT00039
0.45 V
AC Inputs during testing are driven at VDD - 0.5 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIHmin for a logic `1' and VILmax for a logic `0'. Figure 39 AC Testing: Input, Output Waveforms
VLoad +0.1 V VLoad VLoad -0.1 V
Timing Reference Points
VOH -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA Figure 40 AC Testing: Float Waveforms
Crystal Oscillator Mode C XTAL2 2 - 20 MHz C XTAL1
Driving from External Source N.C.
XTAL2
External Oscillator Signal
XTAL1
Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance)
MCS03311
Figure 41 Recommended Oscillator Circuits for Crystal Oscillator at XTAL1 Data Sheet 81 06.99
C505L
Crystal Oscillator Mode
Driving from External Source
C4
XTAL4
N.C.
XTAL4
32.768 MHz
C3
XTAL3
External Oscillator Signal
XTAL3
Crystal Mode : C 3 = 68 pF; C 4 = 33 or 48 pF
MCS04039
Figure 42 Recommended Oscillator Circuits for Real-Time Clock Oscillator at XTAL3 The recommended oscillator circuitry for the Real-Time Clock oscillator configuration using a crystal oscillator of 32.768 KHz.
Data Sheet
82
06.99
C505L
Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Pack)
0.25 min 2 +0.1 -0.05 2.45 max
0.65 0.3 0.08 12.35 17.2 14
1)
0.88
C 0.12
0.1
M
A-B D C 80x
0.2 A-B D 80x 0.2 A-B D H 4x D
A
B
14 1) 17.2
80 1 Index Marking
0.6x45
1) Does not include plastic or metal protrusions of 0.25 max per side
GPM05249
Figure 43 P-MQFP-80-1 Package Outline
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Data Sheet 83
Dimensions in mm 06.99
7max
H
0.15 +0.08 -0.02

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